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  • Exam Name:    Open ROADS Consultant - Big Data & AI
  • Certification:     Huawei Other Certification
  • Vendor Name:  Huawei
  • Exam Code:       OC-15
  • Questions: 65

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NEW QUESTION: 1
Which design restriction applies to Cisco Unified Communications Manager Session Management Edition clustering over the WAN deployment with extended round-trip times in Cisco Unified CM 9.1 and later releases?
A. Only SIP trunk is supported.
B. SIP and H.323 intercluster trunks are supported.
C. SIP trunks and H.323 gateways are supported.
D. A minimum of 1.544 Mb/s bandwidth is required for all traffic between any two nodes in the cluster.
E. Only RSVP agents can be configured and registered to the SME cluster as media resources.
Answer: A
Explanation:
Explanation
Using only SIP trunks in the SME cluster allows you to deploy a "media transparent" cluster where media resources, when required, are inserted by the end or leaf Unified Communications system and never by SME.
Using only SIP trunks also allows you to use extended round trip times (RTTs) between SME nodes when clustering over the WAN.

NEW QUESTION: 2
You are a member of the CsAdministrator group that supports the Microsoft Lync datacenter for the Contoso company. The datacenter consists of two pools:
A Lync 2010 pool named ConPool01 hosts the Central Management Store.
OC-15 Valid Test Format
A Lync 2013 pool named ConPool02.
OC-15 Valid Test Format
You are migrating from Microsoft Lync Server 2010 to Skype for Business Server 2015.
The servers that run ConPool01 suffer a catastrophic failure.
You need to ensure that the users that are hosted on ConPool02 are supported permanently on ConPool02.
What should you do?
A. Run the Install-CsDatabasePowerShell cmdlet, and then run the Move-CsManagementServer cmdlet.
B. Run the Get-CsDatabaseMirrorStatecmdlet, and then run the Invoke-
CSManagement.ServerFailoverPowerShell cmdlet.
C. Run the Set-CsConfigurationStoreLocation cmdlet.
D. Run the Invoke-CsPoolFailoverPowerShell cmdlet.
Answer: B
Explanation:
Explanation/Reference:
Explanation:
References:
https://technet.microsoft.com/en-us/library/jj204678(v=ocs.15).aspx

NEW QUESTION: 3
Which of the following describes a computer processing architecture in which a language compiler or pre- processor breaks program instructions down into basic operations that can be performed by the processor at the same time?
A. Complex-Instruction-Set-Computer (CISC)
B. Reduced-Instruction-Set-Computer (RISC)
C. Super Scalar Processor Architecture (SCPA)
D. Very-Long Instruction-Word Processor (VLIW)
Answer: D
Explanation:
Explanation/Reference:
Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time). These operations are put into a very long instruction word which the processor can then take apart without further analysis, handing each operation to an appropriate functional unit.
The following answer are incorrect:
The term "CISC" (complex instruction set computer or computing) refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way.
Later, it was discovered that, by reducing the full set to only the most frequently used instructions, the computer would get more work done in a shorter amount of time for most applications. Intel's Pentium microprocessors are CISC microprocessors.
The PowerPC microprocessor, used in IBM's RISC System/6000 workstation and Macintosh computers, is a RISC microprocessor. RISC takes each of the longer, more complex instructions from a CISC design and reduces it to multiple instructions that are shorter and faster to process. RISC technology has been a staple of mobile devices for decades, but it is now finally poised to take on a serious role in data center servers and server virtualization. The latest RISC processors support virtualization and will change the way computing resources scale to meet workload demands.
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.
Reference(s) Used for this question:
http://whatis.techtarget.com/definition/0,,sid9_gci214395,00.html
and
http://searchcio-midmarket.techtarget.com/definition/CISC
and
http://en.wikipedia.org/wiki/Superscalar

NEW QUESTION: 4
OC-15 Valid Test Format
A. Option C
B. Option D
C. Option A
D. Option B
Answer: D


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